The CSP Inc., MultiComputer Division designs and builds high-performance cluster computing systems for the defense market. These systems have all the attributes of commerical super-computers but are enhanced with the ruggedization, density, power efficiency and long term support required for the defense market. FastCluster solutions are deployed in a broad array of applications including:


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The FastCluster 3000 SERIES hybrid computing solutions integrate the Freescale 8641D Multicore general purpose processor (GPP), Xilinx Virtex-5 FPGA and Myricom’s 10-Gigabit Ethernet Myri-10G clustering technology on a VXS platform to deliver optimal balance between overall system performance, interoperability, and flexibility.


October 2009:

CSP Inc. announces a rugged 10 Gigabit Ethernet 3000 SERIES VXS Cluster. The cluster includes one or several 10 Gigabit Ethernet VXS pass through modules (VXS-P14), each supporting fourteen (14) 10 GbE SFP+ transceivers on the front panel and fourteen (14) XAUI connections on the VXS backplane. This pass through module connects payloads on the VXS backplane to the 10 Gigabit Ethernet switched fabric.

The new 10 Gigabit Ethernet VXS clusters deliver high-speed connectivity between FPGA and Multi-Core processing nodes and external Ethernet devices, such as data acquisition sensors, RAID disks, and servers.

Read the Press Release (Dated: 10/19/09)

Request additional information to learn more about CSPI and FastCluster Products.

CSP Inc.
43 Manning Road
Billerica, MA 01821
(800) 325-3110

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VITA Members Form VXS Marketing Alliance (08/03/10)

OpenVPXTM System Specification Standard Reaches ANSI Ratification (06/16/10)


The US Department of Defense and other users are mandating improved implementation of open standards and interoperability. VPX specifications have been focused at the board level, but there is also a need for considering system-level requirements to improve interoperability and reduce customization, testing, cost, and risk.

The OpenVPX Systems Specification defines an architecture framework that manages and constrains module and backplane designs, including defining pin outs, and sets interoperability points within VPX while maintaining full compliance with VPX.


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