Accelerate Your Trading Application
With Extreme Low-Latency and Advanced Functions
CSPi’s Myricom DBL technology powers the ARC Series of network adapters, driving down system-level Tick-To-Trade latency and enabling advanced financial trading capabilities. It is a tightly-integrated combination of FPGA firmware and software libraries.
System-level Tick-To-Trade latency
To win against your competition, and make money, you need to squeeze down the time between receiving a market tick favorable to your algorithm and sending out the TRADE order. DBL drives down Tick-To-Trade latency at multiple points in the trading process, allowing your application to avoid slippage and deliver higher fill rates.
Optimize the way you receive market data
First, DBL minimizes Receive Latency by exploiting the parallel processing capabilities of powerful FPGAs to direct subsets of a multi-cast market feed to specified CPU cores, totally bypassing the OS kernel.
At initialization, your application uses our DBL software library for a quick and easy set-up of the selectors, targeting data from a specific address and port to an assigned ring.
Every packet does not need to move into the user space data rings, just the packets your application uses.
Accelerate your application layer
DBL software accelerates trading algorithms with Kernel Bypass Stacks, which move UDP packets directly into user space. Doing that eliminates the cost of CPU context switches and also enables deployment of special-purpose network stacks in user space, which are faster than the general purpose stacks inside the kernel. The DBL has 3 interface options for these faster network stacks:
- Transparent Sockets accelerate stack performance without code changes. Standard socket calls access the low latency DBL stack without recompiling.
- The DBL API accesses a set of Myricom-optimized sockets. It requires a software recompile, with renamed socket calls, but delivers even lower latency.
- Raw Mode allows customers to implement their own custom stacks, using either raw sockets or a proprietary API.
System-level Tick-To-Trade latency
DBL software accelerates outbound order processing by pre-populating the TCP/IP stack in user space, then filling in just the variable information from the application before sending the BUY/SEL order packet to the adapter. This Send Latency is further minimized with extremely efficient PCIe to Ethernet conversion firmware. Each new generation of FPGAs represents faster silicon, making the firmware faster and moving Send (and Receive) Latency closer to zero.
Precise Hardware Timestamps Comply
with Looming Regulations
With DBL firmware, Myricom ARC Series network adapters are able to track latency in real-time with less effort and more accuracy than expensive packet capture devices, using precise hardware timestamps on both ingress and egress packets. This unique capability allows your application to calculate latency without needing to tag TCP/IP orders with UDP sequence numbers, for simplified trading performance verification. You can achieve regulatory compliance, including the upcoming MiFID II requirements, by using DBL to create audit trails of trades with both transmit and receive timestamps. An additional timekeeping option is to use ARC Series adapters with Sniffer10G firmware and software in an adjunct system dedicated to recording trade data.
|Throughput||Sniffer10G provides 100% lossless packet capture and injection of all Ethernet packet sizes.
Supports the maximum possible 10 G packet rate of 14.8 million packets per second.
|Operating System Support||Support for all major Linux distributions as well as Windows 2008R2 and newer.|
|Recommended Server Processor||Intel Haswell-E processors|
The following motherboards are compatible:
Drive trading capabilities with heightened efficiency.